mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis * typical parameter indicates the value for the center of distribution at 2.0v, and not 100% tested. 1 description the m5m5w416c is a family of low voltage 4-mbit static rams organized as 262144-words by 16-bit, fabricated by mitsubishi's high-performance 0.18m cmos technology. the m5m5w416c is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. m5m5w416cwg is packaged in a csp (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) and ball pitch of 0.75mm. it gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. features - single 1.65~2.3v power supply - small stand-by current: 0.2a (2.0v, typ.) - no clocks, no refresh - data retention supply voltage =1.5v - all inputs and outputs are ttl compatible. - easy memory expansion by s1, s2, bc1 and bc2 - common data i/o - three-state outputs: or-tie capability - oe prevents data contention in the i/o bus - process technology: 0.18m cmos - package: 48ball 7.0mm x 8.5mm csp pin configuration a0 ~ a17 dq1 ~ dq16 s1 w oe bc1 address input data input / output chip select input 1 write control input output enable input lower byte (dq1 ~ 8) pin function vcc gnd power supply ground supply bc2 upper byte (dq9 ~ 16) s2 chip select input 2 (top view) outline: 48fja nc: no connection 1 2 3 4 5 6 a b c d e f g dq3 a7 dq1 s2 vcc gnd dq6 a2 s1 dq2 dq4 dq5 dq7 a1 a4 a6 a5 a17 a16 a15 a0 a3 gnd a14 oe bc2 dq15 dq13 dq12 dq10 bc1 dq16 dq14 gnd vcc dq1 1 dq8 w a13 a12 n.c. dq9 n.c. a11 a10 a9 a8 h those are summarized in the part name table below. 30 ma (10mhz) 3ma (1mhz) version, operating temperature part name power supply access time max. stand-by current ratings (max.) active current (2.3v, max) icc1 70c 85c 25c i-version -40 ~ +85c m5m5w416cwg -85hi 1.65 ~ 2.3v 85 ns * typical 40c 25c 40c 15 8 2 1 0.4 0.2 n c
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis 2 function the m5m5w416cwg is organized as 262144-words by 16-bit. these devices operate on a single +1.65~2.3v power supply, and are directly ttl compatible to both input and output. its fully static circuit needs no clocks and no refresh, and makes it useful. the operation mode are determined by a combination of the device control inputs bc1 , bc2 , s1, s2 , w and oe. each mode is summarized in the function table. a write operation is executed whenever the low level w overlaps with the low level bc1 and/or bc2 and the low level s1 and the high level s2. the address(a0~a17) must be set up before the write cycle and must be stable during the entire cycle. a read operation is executed by setting w at a high level and oe at a low level while bc1 and/or bc2 and s1 and s2 are in an active state(s1=l,s2=h). when setting bc1 at the high level and other pins are in an active stage , upper-byte are in a selectable mode in which both reading and writing are enabled, and lower- byte are in a non-selectable mode. and when setting bc2 at a high level and other pins are in an active stage, lower-byte are in a selectable mode and upper- byte are in a non-selectable mode. when setting bc1 and bc2 at a high level or s1 at a high level or s2 at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high-impedance state, allowing or-tie with other chips and memory expansion by bc1, bc2 and s1, s2. the power supply current is reduced as low as 0.2a(25 c , typical), and the memory data can be held at +1.5v power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. block diagram function table mode s2 w h x x high-z bc1 bc2 oe dq1~8 x x non selection dq9~16 icc high-z standby high-z high-z h x l l h din high-z active h h l h read high-z dout active l h h l active h h l active h l high-z high-z active h l h h high-z h l dout h l l read dout active h l din l l x write din active h high-z h h high-z high-z non selection x h h x x standby write h h l l write din active x h l h read high-z active l dout h high-z s1 h l l l l l l l x l l l x x high-z x x non selection high-z standby l l x x high-z x x non selection high-z standby h memory array 262144 words x 16 bits clock generator a 0 a 1 a 16 a 17 s2 bc1 bc2 w oe dq 8 dq 1 dq 16 dq 9 - vcc gnd s1
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis 3 absolute maximum ratings pf 10 v i =gnd, v i =25mvrms, f=1mhz v o = gnd,v o =25mvrms, f=1mhz c i c o symbol parameter limits conditions units a ma ma v icc 1 icc 2 icc 4 v ih v il i o icc 3 v oh i oh = -0.1ma v ol i ol =0.1ma i i v i =0 ~ vcc bc1 and bc2=v ih or s1=v ih or s2=v il or oe=v ih , v i/o =0 ~ vcc vcc+0.2v 0.4 0.7 x vcc -0.2 * 1.3 0.5 0.2 1 30 18 1 3 max typ min dc electrical characteristics f= 10mhz f= 1mhz - - - - - supply voltage input voltage output voltage power dissipation operating temperature storage temperature v mw conditions ta=25c 700 - 65 ~ +150 ratings v cc v i v o p d t a t stg -0.5 * ~ +2.7 -0.2 * ~ vcc + 0.2 (max. 2.7v) 0 ~ vcc symbol parameter units - 40 ~ +85 i-version with respect to gnd f= 10mhz f= 1mhz 1.5 30 18 3 1.5 - with respect to gnd with respect to gnd ( vcc=1.65~ 2.3v, unless otherwise noted) high-level input voltage low-level input voltage high-level output voltage low-level output voltage input leakage current output leakage current active supply current ( ac,mos level ) ( ac,ttl level ) active supply current stand by supply current ( ac,mos level ) ( ac,ttl level ) stand by supply current other inputs= 0 ~ vcc note 1: direction for current flowing into ic is indicated as positive (no mark) note 2: typical parameter indicates the value for the center of distribution at 2.0v, and not 100% tested. capacitance (vcc=1.65 ~ 2.3v, unless otherwise noted) symbol parameter conditions limits max typ min units input capacitance output capacitance * -0.7v in case of ac (pulse width 30ns) bc1 and bc2 0.2v, s1 0.2v, s2 vcc-0.2v other inputs 0.2v or vcc-0.2v output - open (duty 100%) < = < = > = bc1 and bc2=v il , s1=v il ,s2=v ih < = other pins =v ih or v il output - open (duty 100%) bc1 and bc2=v ih or s1=v ih or s2=v il * -0.7v in case of ac (pulse width 30ns) < = < = 10 c c a 0.2 - ~ +85c ~ +25c - 1 ~ +40c - 0.4 2 - 15 (1) s1 vcc - 0.2v, > = other inputs = 0 ~ vcc s2 0.2v, (2) other inputs = 0 ~ vcc bc1 and bc2 vcc - 0.2v s1 0.2v, s2 vcc - 0.2v < = > = (3) > = other inputs = 0 ~ vcc s2 vcc - 0.2v, > = < = ~ +70c - 8 -
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis ac electrical characteristics (vcc=1.65 ~ 2.3v, unless otherwise noted) input rise time and fall time reference level output loads 1.65~2.3v v ih =0.7 x vcc+0.2v, v il =0.2v transition is measured 200mv from steady state voltage.(for ten,tdis) 5ns fig.1,cl=30pf cl=5pf (for ten,tdis) (1) test conditions supply voltage input pulse 1ttl cl dq fig.1 output load including scope and jig capacitance t cr ns t a (s1) t a (oe) t dis (s1) t dis (oe) t en (s1) t en (oe) t v (a) t a (a) 10 4 5 ns ns ns ns ns ns ns ns t a (bc1) t a (bc2) t dis (bc1) t dis (bc2) t dis (bc1) t dis (bc2) ns ns ns ns ns ns 85 30 30 30 30 10 10 5 10 t a (s2) ns t en (s2) 10 ns t dis (s2) ns 30 85 85 hi 4 t su (a-wh) t cw t w (w) t su (a) t su (s1) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) ns ns ns ns ns ns ns ns ns ns ns ns ns ns t su (bc1) t su (bc2) t su (s2) ns 3 0 3 0 85 60 0 7 0 5 5 7 0 7 0 7 0 35 0 0 7 0 symbol parameter read cycle time limits address access time chip select 1 access time chip select 2 access time byte control 1 access time byte control 2 access time output enable access time output disable time after s2 low output disable time after s1 high output disable time after bc1 high max min units (2) read cycle output disable time after bc2 high output disable time after oe high output enable time after s1 low output enable time after s2 high output enable time after bc1 low output enable time after bc2 low output enable time after oe low data valid time after address (3) write cycle max min limits units write cycle time write pulse width address setup time address setup time with respect to w byte control 1 setup time byte control 2 setup time chip select 1 setup time chip select 2 setup time data setup time data hold time write recovery time output disable time from w low output disable time from oe high output enable time from w high output enable time from oe low symbol parameter v oh =v ol =0.9v 85 hi 85 85 85 85
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis s2 (note3) (note3) t su (s2) t en (w) 5 t a (a) t a (bc1) t v (a) t dis (bc1) or t dis (bc1) t a (oe) t en (oe) t dis (oe) t cr t h (d) t su (d) dq 1~16 t su (bc1) or t su (bc2) t en (oe) t dis (oe) t w (w) t rec (w) t su (a) t dis (w) t cw t en (s1) w = "h" level a 0~18 dq 1~16 a 0~18 oe oe w (4)timing diagrams read cycle (note3) (note3) (note3) (note3) valid data write cycle ( w control mode ) data in stable (note3) (note3) t a (s1) t dis (s1) s1 (note3) (note3) bc1 , bc2 t a (bc2) or t en (bc2) t en (bc1) t su (a-wh) s1 (note3) (note3) t su (s1) bc1,bc2 t a (s2) t dis (s2) s2 (note3) (note3) t en (s2)
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis 6 note 3: hatching indicates the state is "don't care". note 4: a write occurs during s1 low, s2 high overlaps bc1 and/or bc2 low and w low. note 6: don't apply inverted phase signal externally when dq pin is in output mode. note 5: when the falling edge of w is simultaneously or prior to the falling edge of bc1 and/or bc2 or the falling t h (d) t su (d) dq 1~16 t su (bc1) or t su (bc2) t rec (w) t su (a) t cw a 0~18 w write cycle (bc control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) s1 edge of s1 or rising edge of s2, the outputs are maintained in the high impedance state. bc1 , bc2 (note3) (note3) s2
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis t h (d) t su (d) dq 1~16 t su (s1) t rec (w) t su (a) t cw a 0~18 w s1 write cycle (s1 control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) bc1 , bc2 (note3) (note3) s2 t h (d) t su (d) dq 1~16 t su (s2) t rec (w) t su (a) t cw a 0~18 w s1 write cycle (s2 control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) bc1,bc2 (note3) (note3) s2 7
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis 8 t su (pd) t rec (pd) ns ms 0.7 x vcc t su (pd) 1.65v 1.65v t rec (pd) bc1 , bc2 vcc-0.2v vcc v 1 .5 vcc (pd) v i (s1) icc (pd) 0.7xvcc bc1 power down characteristics (1) electrical characteristics symbol parameter test conditions limits min typ max units power down supply voltage chip select input s1 power down supply current (2) timing requirements symbol parameter test conditions limits min typ max units power down set up time power down recovery time (3) timing diagram bc control mode v i (bc) byte control input bc1 & bc2 v > = bc2 t su (pd) 1.65v 1.65v t rec (pd) vcc s1 s1 control mode s1 vcc-0.2v > = 0 5 v i (s2) chip select input s2 0.2 0.2v t su (pd) 1.65v 1.65v t rec (pd) vcc s2 s2 control mode s2 0.2v a ~ +40c 0.1 - - ~ +85c ~ +25c - 0.2 0.7 1.5 - 10 (1) s1 vcc - 0.2v, > = other inputs = 0 ~ vcc s2 0.2v, (2) other inputs = 0 ~ vcc bc1 and bc2 vcc - 0.2v s1 0.2v, s2 vcc - 0.2v < = > = (3) > = other inputs = 0 ~ vcc vcc=1.5v 0.7 x vcc 0.7 x vcc 0.7 x vcc 1.65v vcc(pd) 1.5v vcc(pd) 1.65v vcc(pd) 0.7xvcc 1.65v vcc(pd) 1.5v vcc(pd) 1.65v vcc(pd) v 0.2 note 2: typical parameter of icc(pd) indicates the value for the center of distribution at 1.5v, and not 100% tested. < = ~ +70c - 5 -
mitsubishi electric m5m5w416cwg -85hi 2000.11.22 ver. 1.0 4194304 -bit (262144-word by 16-bit) cmos static ram mitsubishi lsis revision history ver. 0.1 / oct.24.2000 initial (-85hi) ver. 0.2 / oct.26.2000 min.1.8v ---> 85ns min.1.7v ---> 100ns (-85hi) ver. 0.3 / oct.26.2000 min.1.65v ---> 85ns ver. 1.0 / nov.22.2000 tsu(d)35ns ---> 45ns
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